Researchers

Antonio González (Principal Investigator)

Antonio González (PhD 1989) is a Full Professor at the Computer Architecture Department of the Universitat Politècnica de Catalunya, Barcelona (Spain), and the director of the Microarchitecture and Compiler research group. He was the founding director of the Intel Barcelona Research Center from 2002 to 2014. His research interest focus on computer architecture, with special emphasis on domain-specific architectures for cognitive computing and graphics processors.

Juan Luis Aragón

Juan Luis Aragón is an Associate Professor in Computer Architecture at the University of Murcia (UMU), Spain. He received his PhD degree in Computer Engineering in 2003 from the UMU. Dr. Aragón has advised 4 PhD theses and has co-authored 50 research papers in major conferences and journals. His research interests are focused on computer architecture, with special emphasis on heterogeneous parallel systems, application-specific accelerators, microarchitecture design, and GPUs.

Carles Aliagas

Carles Aliagas recieved his M.S degree from the the Universitat Politècnica de Catalunya (UPC), in Barcelona, Spain. He joined the Computer Science and Mathematics Department of Rovira i Virgili University in Tarragona where he is currently working as an associate professor. His areas of interest are computer architecture, operating systems and parallelism. His research is focused on memory hierarchies for microprocessors. Contact him at carles.aliagas(at)urv.net

José María Arnau

Jose Maria Arnau received MSc. and PhD on Computer Architecture from the Universitat Politècnica de Catalunya (UPC), in 2011 and 2015 respectively. In 2015 he obtained a position as a postdoctoral researcher in the ARCO group. In 2017 he obtained a position as a distinguished researcher at UPC. He is currently teaching several courses at the Bachelor and Master level and advising seven PhD students. His research interests include hardware accelerators for cognitive computing and GPGPU architectures.

Josep-Llorenç Cruz

Josep-Llorenç Cruz received his M.S. degree from the Universitat Politècnica de Catalunya (UPC), in Barcelona, Catalonia, Spain in 1996. He joined the faculty of the Computer Architecture Department at the Universitat Politècnica de Catalunya (UPC) in 2001 where he is currently a lecturer. His research interests include processor microarchitecture, instruction level parallelism, memory hierarchies for microprocessors, education and ethics in computer science. Contact him at cruz(at)ac.upc.edu

Joan Manuel Parcerisa

Joan-Manuel Parcerisa received his M.S. and Ph.D. degrees in Computer Science from the Universitat Politècnica de Catalunya (UPC), in Barcelona, Spain, in 1993 and 2004 respectively. Since 1994 he is a professor at the Computer Architecture Department in the Universitat Politècnica de Catalunya. His research topics include decoupled access/execute architectures, clustered microarchitectures, predication for O-o-O execution, cache memories, and ultra-low power GPU architectures for mobile devices.

Jordi Tubella

Jordi Tubella is an Associate Professor since 1988 at the Computer Architecture Department of the Universitat Politècnica de Catalunya (UPC). He received the PhD from UPC in 1996 in the area of declarative programming. Currently his research is focused on processor microarchitectures and parallelism. Contact him at jordit(at)ac.upc.edu

Marc Riera

Marc Riera received his B.S degree in Computer Engineering in 2013, his MS degree in MIRI: High Performance Computing in 2015, and his PhD in Computer Architecture in 2020, all from Universitat Politècnica de Catalunya (UPC – BarcelonaTech). He joined the ARCO research group in 2014, and is currently a postdoctoral researcher at ARCO. His research interests focus on the area of Accelerator Architectures, Machine Learning and Near-Data Processing (NDP). Contact him at mriera(at)ac.upc.edu

Franyell Silfa

Franyell Silfa received his BS degree in Computer Engineering in 2010, and his Master’s degree in Computer Engineering in 2011, both from Utah State University (USU), and his Ph.D. in Computer Architecture in 2020 from UPC. He joined the ARCO research group in September 2016 and is currently a postdoctoral researcher at ARCO. His research focuses on the area of energy-efficient architectures for deep learning application. Contact him at fsilfa(at))ac.upc.edu

RaulTaranco

Raúl Taranco (PhD 2024) is a Postdoctoral Researcher at the Huawei Zurich Research Center, working on performance modeling, memory, and large-scale computing systems. He was previously a Postdoctoral Researcher in the ARCO group at the Universitat Politècnica de Catalunya (UPC), where he also completed his PhD under the supervision of Prof. Antonio González and Dr. José-María Arnau on efficient machine vision pipelines. His research interests include memory hierarchies, scalable system design, and hardware–software co-design for high-performance and energy-efficient computing.