An Energy-Efficient Processing Unit for Cognitive Computing
Publications
Journals
M. Sabri, M. Riera and A. González, “Hamun: An Approximate Computing Method to Prolong the Lifespan of ReRAM-Based Accelerators”, Journal of Systems Architecture, Elsevier (ISSN 1383-7621), volume 166, September 2025, article 103444, pp. 1-13. (paper)
B. Khabbazan, M. Sabri, M. Riera and A. González, “An Energy-Efficient Near-Data Processing Accelerator for DNNs to Optimize Memory Accesses”, Journal of Systems Architecture, Elsevier (ISSN 1383-7621), volume 159, February 2025, article 103320, pp. 1-12. (paper)
R. Huerta, and A. González, “SIMIL: SIMple Issue Logic for GPUs”, Microprocessors and Microsystems, Elsevier (ISSN 0141-9331), volume 111, November 2024, article 105105, pp. 1-12. (paper)
D. Pinto, J.-M. Arnau, M. Riera, J.-Ll. Cruz and A. González, “Mixture-of-Rookies: Saving DNN Computations by Predicting ReLU Outputs”, Microprocessors and Microsystems, Elsevier (ISSN 0141-9331), volume 109, Article 105087, September 2024, pp. 1-13.(paper)
D. Pinto, J.-M. Arnau, M. Riera, J.-Ll. Cruz and A. González, “Exploiting Beam Search Confidence for Energy-Efficient Speech Recognition”, The Journal of Supercomputing, Springer (ISSN 0920-8542), volume 80, issue 17, November 2024, pp. 24908-24937. (paper)
R. Taranco, J.-M. Arnau and A. González, “LOCATOR: Low-power ORB Accelerator for Autonomous Cars”, Journal of Parallel and Distributed Computing, vol. 174, April 2023, pp. 32-45. (paper)
R. Yazdani, O. Ruwase, M. Zhang, Y. He, J.-M. Arnau and A. González, “SHARP: An Adaptable, Energy-Efficient Accelerator for Recurrent Neural Networks”, ACM Transactions on Embedded Computing Systems, volume 22, issue 2, March 2023, article no. 30, pp. 1-23. (paper)
A. Segura, J.-M. Arnau and A. González, “Irregular Accesses Reorder Unit: Improving GPGPU Memory Coalescing for Graph-Based Workloads”, The Journal of Supercomputing, volume 79, issue 1, January 2023, pp. 762-787.(paper)
D. Corbalán-Navarro, J.-L. Aragón, M. Anglada, J.-M. Parcerisa and A. González, “Triangle Dropping: An Occluded-Geometry Predictor for Energy-Efficient Mobile GPUs”, ACM Transactions on Architecture and Code Optimization, vol. 19, issue 3, September 2022, article 39, pp. 1-20. (paper)
M. Riera, J.-M. Arnau and A. González, “CREW: Computation Reuse and Efficient Weight Storage for Hardware-accelerated MLPs and RNNs”, Journal of Systems Architecture, volume 129, August 2022, article 102604, pp. 1-12. (paper)
A. Segura, J.-M. Arnau and A. González, “Energy-Efficient Stream Compaction Through Filtering and Coalescing Accesses in GPGPU Memory Partitions”, IEEE Transactions on Computers, volume 71, issue 7, July 2022, pp. 1711-1723. (paper)
M. Anglada, E. de Lucas, J.-M. Parcerisa, J.-L. Aragón A. González, “Dynamic Sampling Rate: Harnessing Frame Coherence in Graphics Applications for Energy-Efficient GPUs”, The Journal of Supercomputing, , volume 78, April 2022, pp. 14940-14964 (paper)
F. Silfa, J.-M. Arnau and A. González, “E-BATCH: Energy-Efficient and High-Throughput RNN Batching”, ACM Transactions on Architecture and Code Optimization, vol. 19, issue 1, January 2022, article 14, pp. 1-23. (paper)
M. Hassanpour, M. Riera and A. González, “A Survey of Near-Data Processing Architectures for Neural Networks”, Machine Learning and Knowledge Extraction, vol. 4, issue 1, January 2022, pp. 66-102. (paper)
M. Riera, J.-M. Arnau and A. González, “DNN Pruning with Principal Component Analysis and Connection Importance Estimation”, Journal of System Architecture, volume 122, January 2022, article 102336, pp. 1-11. (paper)
D. Corbalán-Navarro, J.-L. Aragón, M. Anglada, E. de Lucas, J.-M. Parcerisa and A. González, “Omega-Test: A Predictive Early-Z Culling to Improve the Graphics Pipeline Energy-Efficiency”, IEEE Transactions on Visualization and Computer Graphics, 9 June 2021, p. 1-13. (paper)
D. Pinto, J.-M. Arnau and A. González, “Design and Evaluation of an Ultra Low-Power Human-Quality Speech Recognition System”, ACM Transactions on Architecture and Code Optimization, vol. 17, issue 4, November 2020, article 41, pp. 1:19. (paper)
R. Yazdani, J.-M. Arnau and A. González, “LAWS: Locality-AWare Scheme for Automatic Speech Recognition”, IEEE Transactions on Computers, to appear. 1 August 2020, vol. 69, núm. 8, p. 1197-1208. (paper)
R. Yazdani, J.-M. Arnau and A. González, “A Low-Power, High-Performance Speech Recognition Accelerator”, IEEE Transactions on Computers, volume 68, issue 12, Dec. 2019, pp. 1817-1831. (paper)
M. Riera, J.-M. Arnau and A. González, “CGPA: Coarse-Grained Pruning of Activations for Energy-Efficient RNN Inference”, IEEE Micro, volume 39, issue 5, Sept.-Oct. 2019, pp. 36-45. (paper)
Conferences
P.H.E. Becker, F. Silfa, J.-M. Arnau and A. González, “Caravan: A Hardware/Software Co-Design for Efficient SIMD Neighbor Search on Point Clouds”, Proceedings of the 52nd International Symposium on Computer Architecture, ACM (ISBN 979-8-4007-1261-6), Tokyo (Japan), June 21-25, 2025, pp. 1079-1092. (paper)
R. Huerta and A. González, “GPU Simulation Acceleration via Parallelization”, Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, IEEE (ISBN 979-8-3315-0294-2), Ghent (Belgium), May 11-13, 2025, pp. 390-392. (paper)
R. Taranco, J.-M- Arnau and A. González, “IRIS: Unleashing ISP-Software Cooperation to Optimize the Machine Vision Pipeline”, Proceedings of the 31st International Symposium on High-Performance Computer Architecture, IEEE (ISBN 979-8-3315-0647-6, ISSN 2378-203X), Las Vegas, NV (USA), March 1-5, 2025, pp. 231-245. (paper)
A. Tomás, J.-L. Aragón, J.-M. Parcerisa and A. González, “LIBRA: Memory Bandwidth- and Locality-Aware Parallel Tile Rendering”, Proceedings of the 57th IEEE/ACM International Symposium on Microarchitecture, IEEE (ISBN 979-8-3503-5057-9), Austin, TX (USA), Nov. 2 – 6, 2024, pp. 1058-1072. (paper)
R. Huerta and A. González, “Parallelizing a Modern GPU Simulator”, Proceedings of the 2nd Workshop on Computer Architecture Modeling and Simulation, held in conjunction with 57th IEEE/ACM International Symposium on Microarchitecture, ACM, Austin, TX (USA), Nov. 2 – 6, 2024. (paper)
M. Sabri, M. Riera and A. González, “ReDy: A Novel ReRAM-centric Dynamic Quantization Approach for Energy-efficient CNNs”, Proceedings of the 53rd International Conference on Parallel Processing, ACM (ISBN 979-8-4007-1793-2/24/08), Gotland (Sweden), August 12-15, 2024, pp. 1042-1051 . (paper)
M. Abaie Shoushtary, J.-M. Arnau, J. Tubella and A. González, “Memento: An Adaptive, Compiler-Assisted Register File Cache for GPUs”, Proceedings of the 51st International Symposium on Computer Architecture, IEEE (ISBN 979-8-3503-2658-1), Buenos Aires (Argentina), June 29-July 3, 2024, pp. 978-990. (paper)
R. Taranco, J.-M- Arnau and A. González, “SLIDEX: A Novel Architecture for Sliding Window Processing”, Proceedings of the 38th ACM International Conference on Supercomputing, ACM (ISBN 978-9-4007-0610-3), Kyoto (Japan), June 4-7, 2024, pp. 312-323. (paper)
B. Khabbazan, M. Riera, and A. González, “An Energy-Efficient Near-Data Processing Accelerator for DNNs that Optimizes Data Accesses. (paper)
R. Taranco, J.-M- Arnau and A. González, “δLTA: Decoupling Camera Sampling from Processing to Avoid Redundant Computations in the Vision Pipeline”, Proceedings of the 56th IEEE/ACM International Symposium on Microarchitecture, Toronto (Canada), Oct. 28 – Nov. 1, 2023, pp. 1029-1043. (paper)
P.H.E. Becker, J.-M. Arnau and A. González, “Boosting Point Cloud Search with a Vector Unit”, 2nd Workshop on Robotics Acceleration with Computing Hardware, held in conjunction with the 56th IEEE/ACM International Symposium on Microarchitecture, Toronto (Canada), Oct. 28, 2023. (paper)
R. Huerta, M. Abaie-Shoushtary and A. González, “Analyzing and Improving Hardware Modeling of Accel-Sim”, 1st Workshop on Computer Architecture Modeling and Simulation, held in conjunction with held in conjunction with the 56th IEEE/ACM International Symposium on Microarchitecture, Toronto (Canada), Oct. 28, 2023. (paper)
D. Joseph, J.-L. Aragón, J.-M. Parcerisa and A. González, “Boustrophedonic Frames: Quasi-Optimal L2 Caching for Textures in GPUs”, Proceedings of the 32nd International Conference on Parallel Architectures and Compilation Techniques, Vienna (Austria), Oct. 21-25, 2023, pp. 124-136. (paper)
R. Taranco, J.-M. Arnau and A. González, “SLIDEX: Sliding Window Extension for Image Processing”, Proceedings of the 32nd International Conference on Parallel Architectures and Compilation Techniques, Vienna (Austria), Oct. 21-25, 2023, pp. 332-334. (paper)
B. Khabbazan, M. Riera and A. González, “QeiHan: An Energy-Efficient DNN Accelerator that Leverages Logarithmic Quantization in Near-Data Processing Architectures”, Proceedings of the 32nd International Conference on Parallel Architectures and Compilation Techniques, Vienna (Austria), Oct. 21-25, 2023, pp. 325-326. (paper)
P.H.Exenberger, J.-M. Arnau and A. González, “K-D Bonsai: ISA-Extensions to Compress K-D Trees for Autonomous Driving Tasks”, Proceedings of the 50th International Symposium on Computer Architecture, Orlando, FL (USA), June 17-21, 2023, pp. 275-287. (paper)
M. Abaie Shoushtary, J.-M. Arnau, J. Tubella and A. González, “Lightweight Register File Caching in Collector Units for GPUs”, Proceedings of the 15th Workshop on General Purpose Processing Using GPU, help in conjunction with 28th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Processing, Montreal (Canada), February 25, 2023. (paper).
R. Huerta, J.-M. Arnau and A. González, “Simple Out of Order Core for GPGPUs”, Proceedings of the 15th Workshop on General Purpose Processing Using GPU, help in conjunction with 28th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Processing, Montreal (Canada), February 25, 2023.(paper).
F. Silfa, J.-M. Arnau and A. González, “Exploiting Kernel Compression on BNNs”, Proceedings of the Design Automation and Test Conference, Antwerp (Belgium), April 17-19, 2023. (paper).
R. Taranco, J.-M- Arnau and A. González, “Sliding Window Support for Image Processing in Autonomous Vehicles”, Proceedings of the Workshop on Compute Platforms for Autonomous Vehicles, held in conjunction with the 55th IEEE/ACM International Symposium on Microarchitecture, Chicago IL (USA), Oct. 1, 2022, Oct. 1, 2022. (paper)
D. Joseph, J.-L. Aragón, J.-M. Parcerisa and A. González, “DTexL: Decoupled Raster Pipeline for Texture Locality”, Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, Chicago IL (USA), Oct. 1-5, 2022, Oct. 1, 2022, (paper)
J. Ortiz-Escribano, D. Corbalán-Navarro, J.-L. Aragón and A. González, “MEGsim: A Novel Methodology for Efficient Simulation of Graphics Workloads in GPUs”, Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, Singapore (Republic of Singapore), May 22-24, 2022, pp. 69-78. (paper)
J. Acosta, A. Diavastos and A. González, “XFeatur: Hardware Feature Extraction for DNN Auto-tuning”, Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, Singapore (Republic of Singapore), May 22-24, 2022, pp. 132-34. (paper)
D. Pinto, J.-M. Arnau and A. González, “A Programmable Accelerator for Streaming Automatic Speech Recognition on Edge Devices”, Proceedings of the 6th Workshop on Cognitive Architectures, held in conjunction with 28th Int. Symposium on High-Performance Computer Architecture, Seoul (South Korea), April 2, 2022, pp. 1-3. (paper)
D. Joseph, J.-L. Aragón, J.-M. Parcerisa and A. González, “TCOR: A Tile Cache with Optimal Replacement”, Proceedings of the 28th IEEE International Symposium on High-Performance Computer Architecture, Seoul (South Korea), April 2-6, 2022,pp. 662-675. (paper)
D. Corbalán-Navarro, J.-L. Aragón, M.-M. Parcerisa and A. González, “DTM-NUCA: Dynamic Texture Mapping-NUCA for Energy-Efficient Graphics Rendering”, Proceedings of the 30th Euromicro International Conference on Parallel, Distributed and Network-based Processing, Valladolid (Spain), March 9-11, 2022, pp. 144-151. (paper)
R. Taranco, J.-M. Arnau and A. González, “A Low-Power Hardware Accelerator for ORB Feature Extraction in Self-Driving Cars”, Proceedings of the 33rd IEEE International Symposium on Computer Architecture and High Performance Computing, Belo Horizonte (Brazil), October 26-29, 2021, pp. 11-21. (paper)
D. Corbalán-Navarro, J.-L. Aragón, M. Anglada, E. de Lucas, J.-M. Parcerisa and A. González, “Improving the Energy Efficiency of the Graphics Pipeline by Reducing Overshading”, Proceeding of the Jornadas Sarteco, Málaga (Spain), September 22-24, 2021, pp. 125-134. (paper)
D. Pinto, J.-M. Arnau and A. González, “Design and Evaluation of an Ultra Low-Power Human-Quality Speech Recognition System”, Proceedings of the 16th International Conference on High-Performance Embedded Architectures and Compilers, Budapest (Hungary), Jan. 18-20, 2021. (paper)
F. Silfa, J.-M. Arnau and A. González, “Boosting LSTM Performance Through Dynamic Precision Selection”, Proceedings of the IEEE International Conference on High Performance Computing, Data, and Analytics, Pune (India), Dec. 16-19, 2020, pp. 323-333. (paper)
F. Silfa, G. Dot, J.-M. Arnau and A. González, “Neuron-Level Fuzzy Memoization in RNNs”, Proceedings of the IEEE/ACM International Symposium on Microarchitecture, Columbus OH (USA), Oct. 12-16, 2019, pp. 782-793. (paper)
P.H.Exenberger, J.-M. Arnau, and A. González, “Demystifying power and performance bottlenecks in autonomous driving systems”. Proceedings of the 2020 IEEE International Symposium on Workload Characterization, Beijing (China) 27–29 October 2020, online event, p. 205-215. (paper)
R. Yazdani, J.-M. Arnau and A. González, “Leveraging Run-Time Feedback for Efficient ASR Acceleration”, Proceeding of the 28th International Conference on Parallel Architectures and Compilation Techniques, Seattle, WA (USA), Sept. 21-25, 2019, pp. 462-463. (paper)
Books and Books chapters
P.H.Exenberger, J.-M. Arnau and A. González, “Characterizing Self-Driving Tasks in General-Purpose Architectures”, Advanced Computer Architecture and Compilation for High-performance Embedded Systems, pp. 117-120, 2021. (paper)
A. González, “Trends in Processor Architecture”, Harnessing Performance Variability in Embedded and High Performance Many/Multi-Core Platforms – A Cross-Layer Approach, W. Fornaciari and D. Soudris editors, pp. 23-42, 2019. (paper).
arXiv
R.Huerta and A. González ” Parallelizing a modern GPU simulator “. (paper)
R. Huerta, M. Abaie, J.L. Cruz, A. González ” Analyzing Modern NVIDIA GPU cores”. (paper)
B. Khabbazan, M. Riera and A. González ” Towards Efficient LUT-based PIM: A Scalable and Low-Power Approach for Modern Workloads”. (paper)
M. Sabri M. Riera and A. González “ARAS: An Adaptive Low-Cost ReRAM-Based Accelerator for DNNs “. (paper)
R. Huerta, M. Abaie and A. González, “Analyzing and Improving Hardware Modeling of Accel-Sim”. (paper)
B. Khabbazan, M. Riera and A. González, “DNA-TEQ: An Adaptive Exponential Quantization of Tensors for DNN Inference”. (paper)
N.Narayana, M. Ordoñez, L. Hari, F. Silfa and A. González “ReuseSense: With Great Reuse Comes Greater Efficiency; Effectively Employing Computation Reuse on General-Purpose CPUs”. (paper)
F. Silfa, J.-M. Arnau and A. González, “Saving RNN Computations with a Neuron-Level Fuzzy Memoization Scheme”. (paper)
D. Pinto, J.-M. Arnau and A. González. “Exploiting Beam Search Confidence for Energy-Efficient Speech Recognition”. (paper)
D. Pinto, J.-M. Arnau and A. González, “Mixture-of-Rookies: Saving DNN Computations by Predicting ReLU Outputs”. (paper)
D. Pinto, J.-M. Arnau and A. González, “ASRPU: A Programmable Accelerator for Low-Power Automatic Speech Recognition”. (paper)
